Application-specific Instruction Set Processor Design for Data-intensive Applications
Date of Completion
In this dissertation, we focus on data-intensive applications in wireless communication systems, and propose three novel design methods to improve the energy efficiency, flexibility and performance by exploiting optimization opportunities in both the architecture and algorithm levels. ^ A general approach is first proposed to improve the energy efficiency of ASIPs, targeting one power-critical on-chip component, register files (RFs). We take advantage of the access patterns of register files, and propose a novel compiler-assisted register file partitioning method and register-reallocation approach to reduce the power consumption of register file accessing. We also apply the bit-line splitting technique and drowsy register cell to reduce the overall accessing power consumption without losing the stored data. The proposed method reduces the unit power consumption on each data access, enabling the processor to support extensive data processing under limited energy budget. Next we propose a specific ASIP design for one data-intensive communication algorithm: fast Fourier transformation (FFT). We reconstruct the FFT computation flow into a scalable array structure based on an 8-point butterfly unit (BU), which can be easily expanded along both the horizontal and vertical dimensions for any-point FFT computation. To lower the memory access, we incorporate custom register files to buffer the internal data accesses. The ASIP is implemented on Tensilica's reconfigurable processor platform, which offers considerable flexibility and meets the stringent performance requirements. The third approach we propose is a high-level optimization algorithm to reduce the computational complexity and data access amount of non-binary LDPC decoding. Different from the previous fixed-message truncation methods, it can cut the unnecessary messages adaptively, therefore lowering the computational complexity and providing better decoding quality. To further reduce the computation, another adaptive check node update algorithm is proposed to reduce the number of check nodes updating. Our proposed adaptive decoding algorithm can promote broader application of non-binary LDPC codes in various communication systems. ^ In summary, our three proposed work has successfully integrated application domain expertise with customized computer architecture, and the ASIP we designed and implemented has shown to strike a good balance between efficiency and flexibility. ^
Guan, Xuan, "Application-specific Instruction Set Processor Design for Data-intensive Applications" (2011). Doctoral Dissertations. AAI3476632.