Quantum dot gate nonvolatile memory: Modeling and fabrication
Date of Completion
Engineering, Electronics and Electrical
This dissertation presents novel quantum dot gate nonvolatile memory (QDNVM) devices with larger threshold volt shifts, faster 'write' and longer data retention times compared to conventional silicon nanocrystal gate nonvolatile memories. The floating gate of the QDNVM devices was formed by site-specific self-assembly (SSA) of SiOx-cladded silicon (SiOx-Si) quantum dots (QDs). These monodispersed dots have an average silicon core diameter of 4 nm and a SiOx cladding thickness of 1-2 nm. QDNVM devices demonstrate larger threshold volt shifts than the conventional silicon nanoparticles-based memory devices because of the close-packing and SSA of SiOx-Si QDs significantly increases the amount of charge stored per unit area. SiOx cladding on the QDs enhances the data retention by avoiding the lateral dot-to-dot conduction, thereby avoiding any gate charge leakage path. ^ QDNVM devices exhibit program/erase characteristics similar to the conventional floating gate nonvolatile memory devices. The long-channel QDNVM devices reported here are fabricated on a 10 Ω-cm p-type (100) oriented silicon wafer with a tunnel oxide thickness of about 2 nm grown by thermal oxidation. A 7 nm silicon nitride layer deposited by plasma-enhanced chemical vapor deposition (PECVD) technique serves as the control dielectric. QDNVM devices have been modeled using a SPICE BSIM simulation model. The SPICE model shows good agreement with experimental results. Quantum dots have been characterized using high-resolution transmission electron micrograph showing dot size and cladding thickness. The site-specific self assembly phenomenon has been corroborated with the help of atomic force microscopy. The devices are tested using HP 4156A with a pulse generator. Memory characterization includes program and erase times, cycling endurance, and data retention measurements. Channel Hot Electron Injection (CHEI) was employed for programming the memory devices. Threshold voltage shifts ranging from 0.75 V to 1.5 V were obtained by CHEI with write pulses of 10 V for 1 μs to 1 ms respectively in 5 μm channel QDNVM devices. The threshold voltage shift of QDNVM devices is scarcely degraded after 10 8 seconds demonstrating excellent data retention. The fabrication process is CMOS compatible, and only differs from conventional processing by the step involving SSA of SiOx-Si QDs. QDNVM devices have the potential for economic and promising nonvolatile memory applications. ^
Velampati, Ravi Shankar R, "Quantum dot gate nonvolatile memory: Modeling and fabrication" (2007). Doctoral Dissertations. AAI3276649.