Date of Completion


Embargo Period



II - VI semiconductors, heteroepitaxy, 3- state FET, Non-volatile Memory, high efficiency solar cells

Major Advisor

Faquir Jain

Associate Advisor

John E. Ayers

Associate Advisor

Lei Wang

Associate Advisor

John Chandy

Field of Study

Electrical Engineering


Doctor of Philosophy

Open Access

Open Access


This thesis presents design and fabrication of improved performance FETs, nonvolatile memories, and solar cells. The key feature is the use of wide band gap II-VI quantum well layers and/or quantum dots which are grown using UltraViolet (UV) low temperature Metal-Organic Chemical Vapor Deposition (MOCVD) heteroepitaxy. These layers serve as an insulating substitute for gate insulators such as SiO2 or HfO2. The motivation behind using II-VI lattice-matched gate dielectrics is two-fold: (1) to reduce interface states and their adverse impact on threshold voltage, in particular its variation from device-to-device in sub-22nm structures, and (2) to utilize the higher dielectric constant of ZnMgS with respect to SiO2.

The material structure for this tunneling layer is ZnS/Zn0.95Mg0.05S/ZnS. A 5 nm layer of ZnSe is grown on both sides of this stack to aide with heteroepitaxial adhesion. Auger SIMS surface scan and depth profile data is presented. This ZnSe layer is less than the critical layer thickness therefore is negligible to additional dislocations due to lattice mismatch strain. These II-VI layers are grown at 333o C with a vertical chamber pressure of 250 torrs at 14.25 slm of hydrogen carrier gas. The metal-organic sources used are dimethylzinc (DMZn), dimethylselenide (DMSe), diethylsulfide (DES), and bismethyl-cyclopentadienylmagnesium ((MeCp)2Mg).

Three state FETs have a quantum dot gate comprised of two monolayers of germanium oxide cladded germanium quantum dots (GeOx-Ge). These dots trap charge creating an intermediate state “i” within the FET characteristics. The II-VI tunneling layer provides a smoother transition between ON, i, and OFF states by reducing interface states between the channel and the gate.

Nonvolatile memory FETs transfer charge from the channel to a floating gate. As the gate width approaches sub 22nm, the threshold voltage variation is significantly controlled by interface states between the floating gate and the channel. A heteroepitaxial tunneling layers greatly reduces this threshold voltage variation by reducing the trapped charge states. Substrate material platforms such as InGaAs/InP and Si are been explored. In addition, 3-state quantum dot gate FETs (having QDs assembled on II-VI layers) and nonvolatile memories on SOI have been designed, fabricated, and tested.

II-VI layers, used as the wide energy gap window region, provide efficient solar cell structures. Fabrication of nZnSe-pGe cells is presented. These devices are constructed using a mesa etch and Indium metal top contacts. Photoluminescence characterization (30 K 4x10-5 Torrs) on ZnS(Cl-) films resulted with a bandgap of 2.87 eV. (Run 1857)